/******************************************************************************
*
* MODULE:    Counter_TB.v
* DEVICE:     Test Bench
* PROJECT:   Tarea 1 Diseño Electronico Digital
* AUTHOR:    Ricardo Dávila Castro   
* DATE:      2010 19:35:08
*
* ABSTRACT:  Contador Asc/DEsc Ejercicio 4
*            
*******************************************************************************/
`timescale 1ns / 100ps

`ifndef 	COUNTER_TB
`define    COUNTER_TB


module Counter_TB ;
reg clk_tb;
reg [3:0] inParalela;
reg Captura;
reg Direccion;
reg rst;
  initial
  begin
    clk_tb <= 1'b1;
    forever #5 clk_tb <= ~clk_tb;
  end

  initial 
    begin 

    inParalela = 'b 0111;    
    Captura = 'b 0;
    Direccion = 'b 1;
    rst = 'b 0;
    repeat (2) #3 rst = ~rst; 
    #80 Direccion = ~Direccion;
    #110 Captura = ~Captura;
    #10 Captura = ~Captura;
    #20 Direccion = ~Direccion;
    end
    
 Counter cuenta(.clk(clk_tb),.rst(rst),.EntradaParalela(inParalela),.Captura(Captura),.Direccion(Direccion));


endmodule
`endif